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14/12/10-Bit, 1200 MSPS D/A Converters
Preliminary Technical Data
FEATURES
* * * * * * * * * * 1.8/3.3 V Dual Supply Operation AD9736 SFDR > 53 dBc to fOUT = 600 MHz AD9736 IMD > 65 dBc to fOUT = 600 MHz AD9736 DNL = 1.0 LSB AD9736 INL = 2.0 LSB Low power: 380 mW (IOUTFS = 20 mA; fOUT = 330 MHz) LVDS data interface with on-chip 100 terminations Analog Output: Adjustable 10-30mA (RL=25 to 50 ) On-Chip 1.2 V Reference 160 pin BGA Package
AD9736/AD9735/AD9734
FUNCTIONAL BLOCK DIAGRAM
RESET CLKCLK+
C1 SPI Controller C2 C3 C3 Clock Distribution S3 DATACLK_IN+ DATACLK_INDB[13:0]+ DB[13:0]2X 14,12,10-Bit DAC IOUTB
S1 S2 S3
SDI SDO CSB SCLK
DATACLK_OUT+ DATACLK_OUT-
LVDS Driver
Synchronization
LVDS Receiver
IOUTA
APPLICATIONS
* * * * * Instrumentation Automatic Test Equipment RADAR Avionics Wideband Communications Systems: Point-to-Point Wireless LMDS PA Linearization
C2
C1 S1
Bandgap
Reference Current
S2
VREF
Figure 1. Functional Block Diagram
PRODUCT HIGHLIGHTS
Ultra-low Noise and Intermodulation Distortion (IMD) enable high quality synthesis of wideband signals at intermediate frequencies up to 600 MHz. Double Data Rate (DDR) LVDS data receivers support the maximum conversion rate of 1200 MSPS. Direct pin programmability of basic functions or SPI port access for complete control of all AD9736 family functions. Manufactured on a CMOS process, the AD9736 family uses a proprietary switching technique that enhances dynamic performance. The current output(s) of the AD9736 family can be easily configured for various single-ended or differential circuit topologies.
PRODUCT DESCRIPTION
The AD9736, AD9735, and AD9734 are high performance, high frequency DACs that provide sample rates of up to 1200 MSPS, permitting multi-carrier generation up to their Nyquist frequency. The AD9736 is the 14 bit member of the family, while the AD9735 and the AD9734 are the 12 and 10 bit members, respectively. They include a serial peripheral interface (SPI) port that provides for programming many internal parameters and also enables read-back of status registers. They use a reduced specification LVDS interface to minimize data interface noise that may degrade performance. The output current can be programmed over a range of 10mA to 30mA. The AD9736 family is manufactured on a 0.18m CMOS process and operates from 1.8V and 3.3V supplies for a total power consumption of 380mW in bypass mode. It is supplied in a 160 pin BGA package for reduced package parasitics.
Rev. PrJ 9/7/2004
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
RSET
AD9736/AD9735/AD9734
TABLE OF CONTENTS
AD9736/AD9735/AD9734--Specifications ........................................3 DC SPECIFICATIONS ......................................................................3 DIGITAL SPECIFICATIONS............................................................4 AC SPECIFICATIONS.......................................................................5 EXPLANATION OF TEST LEVELS ................................................5 PIN FUNCTION DESCRIPTIONS......................................................6 PIN CONFIGURATION........................................................................7 PACKAGE OUTLINE.............................................................................9 Ordering Guide ...................................................................................9 TYPICAL PERFORMANCE CHARACTERISTICS........................10 SPI REGISTER MAP ............................................................................14 SPI REGISTER DESCRIPTIONS........................................................15
Preliminary Technical Data
General Description ..............................................................................19 Serial Peripheral Interface................................................................19 AD9736 Data Interface Controllers ....................................................22 AD9736 LVDS Sample Logic...........................................................23 AD9736 SYNC Logic and Controller .............................................25 AD9736 Digital Built-In Self Test........................................................27 AD9736 Analog Control Register .......................................................28 Voltage Reference...................................................................................29 Applications Information .....................................................................30 AD9736 Evaluation Board Schematics ...............................................31 AD9736 Evaluation Board PCB Layout..............................................36
REVISION HISTORY
Revision PrA: Initial Version Revision PrB: Updated data based on initial evaluation results Revision PrC: Updated data for web display and ongoing evaluation results Revision PrD: Added SPI port information Revision PrE: Cleaned up SPI port tables, added AD9736 rev A evaluation board schematics Revision PrF: Added BGA Package Outline Drawing Revision PrG: Added Package Pinout Revision PrH: Added SPI Port Description Revision PrI: Edits for readability and clarity, Added Idd typical values and plots, Updated SPI register tables, Added LVDS and SYNC controller sections, Added pin function table, Added BIST description, Added Analog control section, Added Vref section, Updated eval board schematic and PCB layout Revision PrJ: Update BIST information, Update SPI definition to include SCLK edge change for read operation, Add SPI timing, Annotate schematic to show component values for output circuit, Update ACLR plots, Add PCB fabrication details.
Rev. PrJ | Page 2 of 42
Preliminary Technical Data
AD9736/AD9735/AD9734--SPECIFICATIONS1 DC SPECIFICATIONS
AD9736/AD9735/AD9734
(VDDA33 = VDDD33 = 3.3 V, VDDA18 = VDDD18 = VDDCLK = 1.8 V, MAXIMUM SAMPLE RATE, FS = 20MA, 1X MODE, 25 OHM 1% BALANCED LOAD, UNLESS OTHERWISE NOTED)
AD9736 Parameter RESOLUTION ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Offset Error Gain Error (With Internal Reference) Gain Error (Without Internal Reference) ANALOG OUTPUTS Full Scale Output Current Output Compliance Range Output Resistance Output Capacitance Offset TEMPERATURE DRIFT Gain Reference Voltage REFERENCE ANALOG SUPPLY VOLTAGES DIGITAL SUPPLY VOLTAGES Internal Reference Voltage Output Current VDDA33 VDDA18 VDDD33 VDDD18 Bypass Mode POWER CONSUMPTION FIR Interpolation Filter Enabled Standby Power IDDA33 SUPPLY CURRENTS 1X Mode IDDA18 IDDD33 IDDD18 IDDA33 SUPPLY CURRENTS 2x Mode, Interpoation Enabled IDDA18 IDDD33 IDDD18 3.13 1.70 3.13 1.70 10 1.0 TBD TBD TBD TBD TBD 1.2 100 3.3 1.8 3.3 1.8 380 550 TBD 25 47 10 122 25 47 10 234 3.47 1.90 3.47 1.90 3.13 1.70 3.13 1.70 Temp Test Level Min Typ 14 2.0 1.0 TBD 0.5 0.5 20 30 10 1.0 TBD TBD TBD TBD TBD 1.2 100 3.3 1.8 3.3 1.8 380 550 TBD TBD TBD TBD TBD TBD TBD TBD TBD 3.47 1.90 3.47 1.90 3.13 1.70 3.13 1.70 Max Min AD9735 Typ 12 TBD TBD TBD 0.5 0.5 20 30 10 1.0 TBD TBD TBD TBD TBD 1.2 100 3.3 1.8 3.3 1.8 380 550 TBD TBD TBD TBD TBD TBD TBD TBD TBD 3.47 1.90 3.47 1.90 Max Min AD9734 Typ 10 TBD TBD TBD 0.5 0.5 20 30 Max Bits LSB LSB % FSR % FSR % FSR mA V k pF ppm/C ppm/C ppm/C V nA V V V V mW mW mW mA mA mA mA mA mA mA mA Unit
Table 1: DC Specifications
1
Specifications subject to change without notice Rev. PrJ | Page 3 of 42
AD9736/AD9735/AD9734
DIGITAL SPECIFICATIONS1
Preliminary Technical Data
(VDDA33 = VDDD33 = 3.3 V, VDDA18 = VDDD18 = VDDCLK = 1.8 V, MAXIMUM SAMPLE RATE, FS = 20MA, 1X MODE, 25 OHM 1% BALANCED LOAD, UNLESS OTHERWISE NOTED)
Parameter Temp Test Level AD9736,35,34 Min Input voltage range, Via or Vib Input differential threshold Input differential hysteresis Receiver differential input impedance LVDS input rate LVDS data Bit Error Rate Input voltage range, Via or Vib Input differential threshold Input differential hysteresis Receiver differential input impedance Maximum Clock Rate Output voltage high, Voa or Vob Output voltage low, Voa or Vob Output differential voltage Output offset voltage Output impedance, single ended LVDS CLOCK OUTPUT (DATACLK_OUT+, DATACLK_ OUT-) DATACLK_OUT+ = Voa, DATACLK_OUT- = Vob 100 ohm termination Ro mismatch between A & B Change in |Vod| between `0' and `1' Change in Vos between `0' and `1' Output current - Driver shorted to ground Output current - Drivers shorted together Power-off output leakage Maximum Clock Rate Differential peak-to-peak Voltage Common Mode Voltage Maximum Clock Rate Maximum Clock Rate (SCLK, 1/tSCLK) Minimum pulse width high, tPWH Minimum pulse width low, tPWL Minimum SDIO and CSB to SCLK setup, tDS Minimum SCLK to SDIO hold, tDH Maximum SCLK to valid SDIO and SDO, tDV Minimum SCLK to invalid SDIO and SDO, tDNV 825 -100 20 80 1200 TBD 825 -100 20 80 600 1375 1025 150 1150 80 200 100 250 1250 120 10 25 25 20 4 TBD 600 800 400 1200 20 20 20 10 5 20 5 120 1575 100 120 Typ Max 1575 100 mV mV mV MSPS Err/Bit mV mV mV MHz mV mV mV mV % mV mV mA mA mA MHz mV mV MHz MHz ns ns ns ns ns ns Unit
LVDS DATA INPUTS (DB[13:0]+, DB[13:0]-) DB+ = Via, DB- = Vib
LVDS CLOCK INPUT (DATACLK_IN+, DATACLK_IN-) DATACLK+ = Via, DATACLK- = Vib
DAC CLOCK INPUT (CLK+, CLK-)
SERIAL PERIPHERAL INTERFACE
Table 2: Digital Specifications
1
LVDS Drivers and Receivers are compliant to the IEEE-1596 Reduced Range Link, unless otherwise noted Rev. PrJ | Page 4 of 42
Preliminary Technical Data
AC SPECIFICATIONS
AD9736/AD9735/AD9734
(VDDA33 = VDDD33 = 3.3 V, VDDA18 = VDDD18 = VDDCLK = 1.8 V, MAXIMUM SAMPLE RATE, FS = 20MA, 1X MODE, 25 OHM 1% BALANCED LOAD, UNLESS OTHERWISE NOTED)
AD9736 Parameter Maximum Update Rate Output Settling Time (tst) (to 0.025%) DYNAMIC PERFORMANCE Output Rise Time (10% to 90%) Output Fall Time (90% to 10%) Output Noise (IoutFS=20mA) fDAC = 1200 MSPS, fOUT = 50 MHz SPURIOUS FREE DYNAMIC RANGE (SFDR) fDAC = 1200 MSPS, fOUT = 100 MHz fDAC = 1200 MSPS, fOUT = 316 MHz fDAC = 1200 MSPS, fOUT = 550 MHz fDAC = 1200 MSPS, fOUT = 50 MHz Two Tone Intermodulation Distortion (IMD) fDAC = 1200 MSPS, fOUT = 100 MHz fDAC = 1200 MSPS, fOUT = 316 MHz fDAC = 1200 MSPS, fOUT = 550 MHz fDAC = 1200 MSPS, fOUT = 50 MHz Noise Spectral Density (NSD) fDAC = 1200 MSPS, fOUT = 100 MHz fDAC = 1200 MSPS, fOUT = 316 MHz fDAC = 1200 MSPS, fOUT = 550 MHz Temp Test Level Min Typ 1200 TBD TBD TBD TBD 80 77 63 55 85 84 74 65 -165 -164 -158 -155 Max Min AD9735 Typ 1200 TBD TBD TBD TBD Max Min AD9734 Typ 1200 TBD TBD TBD TBD Max Unit MSPS ns ns ns pA/rtHz dBc dBc dBc dBc dBc dBc dBc dBc dBm/Hz dBm/Hz dBm/Hz dBm/Hz
Table 3: AC Specifications
EXPLANATION OF TEST LEVELS
TEST LEVEL
I II III IV V VI 100% production tested. 100% production tested at +25C and guaranteed by design and characterization at specified temperatures. Sample Tested Only Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at +25C and guaranteed by design and characterization for industrial temperature range.
Rev. PrJ | Page 5 of 42
AD9736/AD9735/AD9734
PIN FUNCTION DESCRIPTIONS
Pin No.
A1, A2, A3, B1, B2, B3, C1, C2, C3, D2, D3 A4, A5, A6, A9, A10, A11, B4, B5, B6, B9, B10, B11, C4, C5, C6, C9, C10, C11, D4, D5, D6, D9, D10, D11 A7, B7, C7, D7 A8, B8, C8, D8 A12, A13, B12, B13, C12, C13, D12, D13 A14, K1 B14 C14 D1, E2, E3, E4, F2, F3, F4, G1, G2, G3, G4 D14 E1, F1 E11, E12, F11, F12, G11, G12 E13
Preliminary Technical Data
Description
1.8V, Clock supply Analog supply ground DAC negative output, 10mA to 30mA full scale output current DAC positive output, 10mA to 30mA full scale output current 3.3V Analog supply Do Not Connect Nominal 1.2V reference tied to analog ground via 10kohm resistor to generate a 120uA reference current Bandgap voltage reference I/O, tie to analog ground via 1nF capacitor, output impedance approximately 5kohms Clock supply ground Factory test, output current proportional to absolute temperature, approximately 10uA at 25C with approximately 20nA/C slope Negative, Positive DAC clock input (DACCLK) Analog supply ground shield If PIN_MODE = 0, IRQ: Active low open-drain interrupt request output, pull up to VDD3.3 with 10kohm resistor If PIN_MODE = 1, UNSIGNED: Digital input pin where 0 = two's complement input data format, 1 = unsigned If PIN_MODE = 0, RESET: 1 resets the AD9736 If PIN_MODE = 1, PD: 1 puts the AD9736 in the power down state See SPI and PIN Mode sections for pin description See SPI and PIN Mode sections for pin description See SPI and PIN Mode sections for pin description See SPI and PIN Mode sections for pin description 1.8V Digital supply Digital supply ground Negative, Positive data input bit 13 (MSB), reduced swing LVDS 0, SPI Mode, SPI enabled 1, PIN Mode, SPI disabled, direct pin control 3.3V Digital supply Negative, Positive data input bit 12, reduced swing LVDS Negative, Positive data input bit 0 (LSB), reduced swing LVDS Negative, Positive data input bit 11, reduced swing LVDS Negative, Positive data input bit 1, reduced swing LVDS Negative, Positive data input bit 2, reduced swing LVDS Negative, Positive data input bit 3, reduced swing LVDS Negative, Positive data input bit 4, reduced swing LVDS Negative, Positive data input bit 5, reduced swing LVDS Negative, Positive output clock, reduced swing LVDS Negative, Positive data input clock, reduced swing LVDS Negative, Positive data input bit 6, reduced swing LVDS Negative, Positive data input bit 7, reduced swing LVDS Negative, Positive data input bit 8, reduced swing LVDS Negative, Positive data input bit 9, reduced swing LVDS Negative, Positive data input bit 10, reduced swing LVDS
Name
VDDC VSSA IOUTB IOUTA VDDA DNC I120 VREF VSSC IPTAT CLK-, CLK+ VSSA IRQ / UNSIGNED
E14 F13 F14 G13 G14 H1, H2, H3, H4, H11, H12, H13, H14, J1, J2, J3, J4, J11, J12, J13, J14 K2, K3, K4, K11, K12, L2, L3, L4, L5, L6, L9, L10, L11, L12, M3, M4, M5, M6, M9, M10, M11, M12 K13, K14 L1 L7, L8, M7, M8, N7, N8, P7, P8 L13, L14 M2, M1 M13, M14 N1, P1 N2, P2 N3, P3 N4, P4 N5, P5 N6, P6 N9, P9 N10, P10 N11, P11 N12, P12 N13, P13 N14, P14
RESET / PD CSB / 2x SDIO / FIFO SCLK / FSC0 SDO / FSC1 VDD VSS DB<13> -, + PIN_MODE VDD33 DB<12> -, + DB<0> -, + DB<11> -, + DB<1> -, + DB<2> -, + DB<3> -, + DB<4> -, + DB<5> -, + DATACLK_OUT -, + DATACLK_IN -, + DB<6> -, + DB<7> -, + DB<8> -, + DB<9> -, + DB<10> -, +
Rev. PrJ | Page 6 of 42
Preliminary Technical Data
PIN CONFIGURATION
1 A B C D E F G H J K L M N P VDDA, 3.3V, Analog Supply VSSA, Analog Supply Ground VSSA, Analog Supply Ground Shield 2 3 4 5 6 7 8 9 10 11 12 13 14
AD9736/AD9735/AD9734
1 A B C D E F G H J K L M N P VDDC, 1.8V, Clock Supply VSSC, Clock Supply Ground 2 3 4 5 6 7 8 9 10 11 12 13 14
Figure 3. AD9736 Clock Supply Pins (TOP view)
Figure 2. AD9736 Analog Supply Pins (TOP view)
1 A B C D E F G H J K L M N P VDD, 1.8V Digital Supply VDD33, 3.3V Digital Supply VSS Digital Supply Ground 2 3 4 5 6 7 8 9 10 11 12 13 14
A B C D CLKN E CLKP F G H J K L LVDS0 (LSB) M N P
LVDSCLKP,N OUT DCLKP,N IN LVDS10 LVDS1 LVDS3 LVDS4 LVDS6 LVDS7 LVDS8 LVDS5 LVDS9 LVDS
1
2
3
4
5
6
7
8
9 10 11 12 13 14
LVDS13 (MS LVDS12 LVDS11
Figure 4. AD9736 Digital Supply Pins (TOP view) Figure 5. AD9736 Digital LVDS Inputs, Clock I/O (TOP view)
Rev. PrJ | Page 7 of 42
AD9736/AD9735/AD9734
IOUTN IOUTP
Preliminary Technical Data
1 A B C D E F G H J K PIN_MODE L M N P
2
3
4
5
6
7
8
9 10 11 12 13 14 PIN_MODE=0, SPI ENABLED I120 VREF IPTAT IRQ CSB SCLK RESET SDIO SDO
PIN_MODE=1, SPI DISABLED UNSIGNED 2x FSCO PD FIFO FSC1
Figure 6. AD9736 Analog I/O and SPI Control Pins (TOP view)
Rev. PrJ | Page 8 of 42
Preliminary Technical Data
PACKAGE OUTLINE
a
160-Lead Chip Scale Ball Grid Array [CSPBGA] (BC-160) Dimensions shown in millimeters
AD9736/AD9735/AD9734
12.00 BSC SQ
A1 CORNER INDEX AREA
14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P
BALL A1 INDICATOR TOP VIEW 10.40 BSC BOTTOM VIEW
0.80 BSC
DETAIL A 1.40 MAX
DETAIL A
1.00 0.85
0.25 MIN 0.55 SEATING 0.50 PLANE 0.45 BALL DIAMETER COMPLIANT WITH JEDEC STANDARDS MO-205-AE. 0.12 MAX COPLANARITY
Figure 7. AD9736 BGA Package Outline Drawing
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Ordering Guide
Model AD9736BBC AD9736-EB Temperature Range -40C to +85C (Ambient) 25C (Ambient) Description 160-Lead Chip Scale BGA Evaluation Board
Table 4: Ordering Guide
Rev. PrJ | Page 9 of 42
AD9736/AD9735/AD9734
TYPICAL PERFORMANCE CHARACTERISTICS
1 0.8 0.6 0.4 Error - LSB 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 2048 4096 6144 8192 Code 10240 12288
Preliminary Technical Data
14336
16384
Figure 8. AD9736, Typical INL
0.5
0.3
0.1 Error - LSB
-0.1
-0.3
-0.5
-0.7 0 2048 4096 6144 8192 Code 10240 12288 14336 16384
Figure 9. AD9736, Typical DNL
3rd Order IMD With Respect to Fout (20mA FS)
800MSPS 90 85 80 IMD - [dBc] 75 70 65 60 55 50 0 50 100 150 200 250 300 350 400 450 500 550 600 Fout - [MHz] 1GSPS 1.2GSPS
Figure 10. AD9736, 3rd Order IMD vs. Fout and Sample Rate
Rev. PrJ | Page 10 of 42
Preliminary Technical Data
NSD Comparison With 1-Tone and 8-Tones at 1.2GSPS 1 Tone -150 -152 -154 -156 NSD - dBm/Hz -158 -160 -162 -164 -166 -168 -170 0 100 200 300 400 500 600 700 Fout - Mhz 8 Tones
AD9736/AD9735/AD9734
Figure 11. AD9736, Noise Spectral Density (NSD) vs. Fout at 1.2GSPS
In- Band SFDR With Respect to Fout (20mA FS)
800MSPS 90 85 80 SFDR - [dBc] 75 70 65 60 55 50 0 50 100 150 200 250 300 350 400 450 500 550 600 Fout - [MHz] 1GSPS 1.2GSPS
Figure 12. AD9736, In Band SFDR vs. Fout and Sample Rate
Rev. PrJ | Page 11 of 42
AD9736/AD9735/AD9734
Preliminary Technical Data
Figure 13. AD9736, WCDMA carrier at 134.83MHz, fdata=491.52MSPS
Figure 14. AD9735, WCDMA carrier at 134.83MHz, fdata=491.52MSPS
Figure 15. AD9734, WCDMA carrier at 134.83MHz, fdata=491.52MSPS
Rev. PrJ | Page 12 of 42
Preliminary Technical Data
AD9736/AD9735/AD9734
AD9736 Power Consumption 1x Mode With Respect to Clock Speed
VDDD_1.8 0.5 0.45 0.4 0.35 Power - W 0.3 0.25 0.2 0.15 0.1 0.05 0 0 250
VDDD_33
VDDA_1.8
VDDA_3.3
total
500
750 FCLK- MHz
1000
1250
1500
Figure 16. AD9736 Power vs. Clock Frequency
AD9736 Power Consumption 2x Mode With Respect to Clock Speed
VDDD_1.8 0.7 0.6 0.5 Power - W 0.4 0.3 0.2 0.1 0 0 250
VDDD_33
VDDA_1.8
VDDA_3.3
total
500
750 FCLK- MHz
1000
1250
1500
Figure 17. AD9736 Power vs. Clock Frequency in 2x Mode
Rev. PrJ | Page 13 of 42
AD9736/AD9735/AD9734
SPI REGISTER MAP
ADR DEC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 31
Preliminary Technical Data
PIN Default MODE (HEX) (HEX)
00 00 02 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00
ADR HEX
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 1F
Register Name
MODE IRQ FSC_1 FSC_2 LVDS_CNT1 LVDS_CNT2 LVDS_CNT3 SYNC_CNT1 SYNC_CNT2 RESERVED RESERVED RESERVED RESERVED RESERVED ANA_CNT1 ANA_CNT2 RESERVED BIST_CNT BIST<7:0> BIST<15:8> BIST<23:16> BIST<31:24> CCLK_DIV VERSION
Bit 7
SDIO_DIR LVDS SLEEP FSC<7> MSD<3> SD<3> LSURV FIFOSTAT3 SSURV
Bit 6
LSBFIRST SYNC
Bit 5
RESET CROSS
Bit 4
LONG_INS RESV'D
Bit 3
2X MODE IE_LVDS
Bit 2
FIFO MODE IE_SYNC
Bit 1
DATAFRMT IE_CROSS FSC<9>
Bit 0
PD RESV'D FSC<8> FSC<0> MHD<0> CHECK LTRH<0> PHOF<0> STRH<0>
FSC<6> MSD<2> SD<2> LAUTO FIFOSTAT2 SAUTO
FSC<5> MSD<1> SD<1> LFLT<3> FIFOSTAT1 SFLT<3>
FSC<4> MSD<0> SD<0> LFLT<2> FIFOSTAT0 SFLT<2>
FSC<3> MHD<3> LCHANGE LFLT<1> VALID SFLT<1>
FSC<2> MHD<2> ERR_HI LFLT<0> SCHANGE SFLT<0>
FSC<1> MHD<1> ERR_LO LTRH<1> PHOF<1> RESV'D
MSEL<1> HDRM<7>
MSEL<0> HDRM<6> HDRM<5> HDRM<4> HDRM<3>
TRMBG<2> HDRM<2>
TRMBG<1> HDRM<1>
TRMBG<0> HDRM<0>
C0 CA
C0 CA
SEL<1>
SEL<0>
SIG_READ
LVDS_EN
SYNC_EN
CLEAR
00
00
RESV'D VER<5>
RESV'D VER<4>
RESV'D VER<3>
RESV'D VER<2>
CCD<3> VER<1>
CCD<2> VER<0>
CCD<1> RES10
CCD<0> RES12
00
00
Note: Write `0' to unspecified or reserved bit locations. Reading these bits will return unknown values.
Table 5. SPI Register Map
Rev. PrJ | Page 14 of 42
Preliminary Technical Data
SPI REGISTER DESCRIPTIONS
REG 00 -> MODE Reading REG 00 returns previously written values for all defined register bits unless otherwise noted. Reset value in bold text. ADR 0x00 Name MODE Bit 7 SDIO_DIR Bit 6 LSB/MSB Bit 5 RESET Bit 4 LONG_INS Bit 3 2X MODE
AD9736/AD9735/AD9734
Bit 2 FIFO MODE
Bit 1 DATAFRMT
Bit 0 PD
SDIO_DIR
: WRITE ->
0, Input only per SPI standard 1, Bidirectional per SPI standard 0, MSB first per SPI standard 1, LSB first per SPI standard NOTE: Only change LSB/MSB order in single byte instructions to avoid erratic behavior due to bit order errors 0, Execute software reset of SPI and controllers, reload default register values EXCEPT registers 0x00 and 0x04 1, Set software reset prior to writing `0' to execute the software reset 0, Short (single-byte) instruction word 1, Long (two-byte) instruction word, not necessary since the maximum internal address is REG31 (0x1F) 0, Disable 2x Interpolation Filter 1, Enable 2x Interpolation Filter 0, Disable FIFO synchronization 1, Enable FIFO synchronization 0, Signed input DATA with midscale = 0x0000 1, Unsigned input DATA with midscale = 0x2000 0, Enable LVDS Receiver, DAC and Clock Circuitry 1, Power down LVDS Receiver, DAC and Clock Circuitry
LSBFIRST
: WRITE ->
RESET
: WRITE->
LONG_INS
: WRITE ->
2X_MODE
: WRITE ->
FIFO_MODE
: WRITE ->
DATAFRMT
: WRITE ->
PD
: WRITE ->
REG 01 -> Interrupt Request (IRQ) Reading REG 01 returns previously written values for all defined register bits unless otherwise noted. Reset value in bold text. ADR 0x01 LVDS Name IRQ : WRITE -> : READ -> Bit 7 LVDS Don't Care 0, No active LVDS receiver interrupt 1, Interrupt in LVDS receiver occurred Don't Care 0, No active SYNC logic interrupt 1, Interrupt in SYNC logic occurred Don't Care 0, No active CROSS logic interrupt 1, Interrupt in CROSS logic occurred 0, Reset LVDS receiver interrupt and disable future LVDS receiver interrupts 1, Enable LVDS receiver interrupt to activate IRQ pin 0, Reset SYNC logic interrupt and disable future SYNC logic interrupts 1, Enable SYNC logic interrupt to activate IRQ pin 0, Reset CROSS logic interrupt and disable future CROSS logic interrupts 1, Enable CROSS logic interrupt to activate IRQ pin Bit 6 SYNC Bit 5 CROSS Bit 4 RESV'D Bit 3 IE_LVDS Bit 2 IE_SYNC Bit 1 IE_CROSS Bit 0 RESV'D
SYNC
: WRITE -> : READ ->
CROSS
: WRITE -> : READ ->
IE_LVDS
: WRITE ->
IE_SYNC
: WRITE ->
IE_CROSS
: WRITE ->
Rev. PrJ | Page 15 of 42
AD9736/AD9735/AD9734
Preliminary Technical Data
REG 02, 03 -> Full Scale Current (FSC) Reading REG 02 & 03 return previously written values for all defined register bits unless otherwise noted. Reset value in bold text. ADR 0x02 0x03 Name FSC_1 FSC_2 Bit 7 SLEEP FSC<7> FSC<6> FSC<5> FSC<4> FSC<3> FSC<2> Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 FSC<9> FSC<1> Bit 0 FSC<8> FSC<0>
SLEEP
: WRITE ->
0, Enable DAC output 1, Set DAC output current to 0mA 0x000, 10mA full scale output current 0x200, 20mA full scale output current 0x3FF, 30mA full scale output current
FSC<9:0>
: WRITE ->
NOTE: Iout = (72 + 192 * ( FSC<9:0> / 1024 ) ) * I120 where I120 = Vref / R120u, for example 1.2V / 10k = 120uA
REG 04, 05, 06 -> LVDS Controller (LVDS_CNT) Reading REG 04, 05 & 06 return previously written values for all defined register bits unless otherwise noted. Reset value in bold text. ADR 0x04 0x05 0x06 MSD<3:0> Name LVDS_CNT1 LVDS_CNT2 LVDS_CNT3 : WRITE -> : READ -> Bit 7 MSD<3> SD<3> LSURV Bit 6 MSD<2> SD<2> LAUTO Bit 5 MSD<1> SD<1> LFLT<3> Bit 4 MSD<0> SD<0> LFLT<2> Bit 3 MHD<3> LCHANGE LFLT<1> Bit 2 MHD<2> ERR_HI LFLT<0> Bit 1 MHD<1> ERR_LO LTRH<1> Bit 0 MHD<0> CHECK LTRH<0>
0x0, Set setup delay for the measurement system If ( LAUTO == 1) the latest measured value for the setup delay If ( LAUTO == 0) read back of the last SPI write to this bit 0x0, Set hold delay for the measurement system If ( LAUTO == 1) the latest measured value for the hold delay If ( LAUTO == 0) read back of the last SPI write to this bit 0x0, Set sample delay If ( LAUTO == 1) the result of a measurement cycle is stored in this register If ( LAUTO == 0) read back of the last SPI write to this bit 0, No change from previous measurement 1, Change in value from the previous measurement NOTE: The average filter and the threshold detection are not applied to this bit One of the 15 LVDS inputs is above the input voltage limits of the IEEE reduce link spec. One of the 15 LVDS inputs is below the input voltage limits of the IEEE reduced link spec. 0, Phase measurement - sampling in the previous or following DATA cycle 1, Phase measurement - sampling in the correct DATA cycle 0, The controller stops after completion of the current measurement cycle 1, Continuous measurements are taken and an interrupt is issued if the clock alignment drifts beyond the threshold value 0, Sample delay is not automatically updated 1, Continuously starts measurement cycles and updates the sample delay according to the measurement NOTE: LSURV (REG06 Bit 7) must be set to 1 and the LVDS IRQ (REG01 Bit 3) must be set to 0 for AUTO mode 0x0, Average filter length, Delay = Delay + Delta Delay / 2^ LFLT<3:0>, values greater than 12 (0x0C) are clipped to 12
MHD<3:0>
: WRITE -> : READ ->
SD<3:0>
: WRITE-> : READ ->
LCHANGE
: READ ->
ERR_HI ERR_LO
: READ -> : READ ->
CHECK
: READ ->
LSURV
: WRITE ->
LAUTO
: WRITE ->
LFLT<3:0>
: WRITE ->
Rev. PrJ | Page 16 of 42
Preliminary Technical Data
LTRH<2:0> : : WRITE -> 000, Set auto update threshold values
AD9736/AD9735/AD9734
REG 07, 08 -> SYNC Controller (SYNC_CNT) Reading REG 07 & 08 return previously written values for all defined register bits unless otherwise noted. Reset value in bold text. ADR 0x07 0x08 FIFOSTAT<2:0> Name SYNC_CNT1 SYNC_CNT2 : READ -> Bit 7 FIFOSTAT3 SSURV Bit 6 FIFOSTAT2 SAUTO Bit 5 FIFOSTAT1 SFLT<3> Bit 4 FIFOSTAT0 SFLT<2> Bit 3 VALID SFLT<1> Bit 2 SCHANGE SFLT<0> Bit 1 PHOF<1> RESV'D Bit 0 PHOF<0> STRH<0>
Position of FIFO read counter, range from 0 to 7 0, SYNC logic OK 1, Error in SYNC logic 0, FIFOSTAT<3:0> is not valid yet 1, FIFOSTAT<3:0> is valid after a reset 0, No change in FIFOSTAT<3:0> 1, FIFOSTAT<3:0> has changed since the previous measurement cycle when SSURV = 1 (surveillance mode active) 00, Change the readout counter Current setting of the readout counter (PHOF<1:0>) in surveillance mode (SSURV = 1) after an interrupt Current calculated optimal readout counter value in AUTO mode (SAUTO = 1) 0, The controller stops after completion of the current measurement cycle 1, Continuous measurements are taken and an interrupt is issued if the readout counter drifts beyond the threshold value 0, Readout counter (PHOF<3:0>) is not automatically updated 1, Continuously starts measurement cycles and updates the readout counter according to the measurement NOTE: SSURV (REG08 Bit 7) must be set to 1 and the SYNC IRQ (REG01 Bit 2) must be set to 0 for AUTO mode 0x0, Average filter length, FIFOSTAT = FIFOSTAT + Delta FIFOSTAT / 2 ^ SFLT<3:0>, values greater than 12 (0x0C) are clipped to 12 0, If FIFOSTAT<2:0> = 0 | 7, generate a SYNC interrupt 1, If FIFOSTAT<2:0> = 0 | 1 | 6 | 7, generate a SYNC interrupt
FIFOSTAT<3>
: READ ->
VALID
: READ ->
SCHANGE
: READ ->
PHOF<1:0>
: WRITE -> : READ ->
SSURV
: WRITE ->
SAUTO
: WRITE ->
SFLT<3:0>
: WRITE ->
STRH<0>
: WRITE ->
REG 14, 15 -> Analog Control (ANA_CNT) Reading REG 14 & 15 return previously written values for all defined register bits unless otherwise noted. Reset value in bold text. ADR 0x0E 0x0F Name ANA_CNT1 ANA_CNT2 Bit 7 MSEL<1> HDRM<7> Bit 6 MSEL<0> HDRM<6> HDRM<5> HDRM<4> HDRM<3> Bit 5 Bit 4 Bit 3 Bit 2 TRMBG<2> HDRM<2> Bit 1 TRMBG<1> HDRM<1> Bit 0 TRMBG<0> HDRM<0>
MSEL<1:0>
: WRITE ->
00, Mirror roll off frequency control = bypass 01, Mirror roll off frequency control = narrowest bandwidth 10, Mirror roll off frequency control = medium bandwidth 11, Mirror roll off frequency control = widest bandwidth NOTE: See plot in the applications section 000, Bandgap temperature characteristic trim NOTE: See plot in the applications section 0xCA, Output stack headroom control HDRM<7:4> set reference offset from Vdd3v (vcas centering) HDRM<3:0> set overdrive (current density) trim (temperature tracking) Note: Set to 0xCA for optimum performance
TRMBG<2:0>
: WRITE ->
HDRM<7:0>
: WRITE ->
Rev. PrJ | Page 17 of 42
AD9736/AD9735/AD9734
Preliminary Technical Data
REG 17, 18, 19, 20, 21 -> Built-in Self Test Control (BIST_CNT) Reading REG17, 18, 19, 20 & 21 return previously written values for all defined register bits unless otherwise noted. Reset value in bold text. ADR 0x11 0x12 0x13 0x14 0x15 Name BIST_CNT BIST<7:0> BIST<15:8> BIST<23:16> BIST<31:24> Bit 7 SEL<1> BIST<7> BIST<15> BIST<23> BIST<31> Bit 6 SEL<0> BIST<6> BIST<14> BIST<22> BIST<30> Bit 5 SIG_READ BIST<5> BIST<13> BIST<21> BIST<29> BIST<4> BIST<12> BIST<20> BIST<28> BIST<3> BIST<11> BIST<19> BIST<27> Bit 4 Bit 3 Bit 2 LVDS_EN BIST<2> BIST<10> BIST<18> BIST<26> Bit 1 SYNC_EN BIST<1> BIST<9> BIST<17> BIST<25> Bit 0 CLEAR BIST<0> BIST<8> BIST<16> BIST<24>
SEL<1:0>
: WRITE ->
00, Write result of the LVDS Phase 1 BIST to BIST<31:0> 01, Write result of the LVDS Phase 2 BIST to BIST<31:0> 10, Write result of the SYNC Phase 1 BIST to BIST<31:0> 11, Write result of the SYNC Phase 2 BIST to BIST<31:0> 0, No action 1, Enable BIST signature readback 0, No action 1, Enable LVDS BIST 0, No Action 1, Enable SYNC BIST 0, No Action 1, Clear all BIST registers Results of the Built-in Self Test
SIG_READ
: WRITE ->
LVDS_EN
: WRITE->
SYNC_EN
: WRITE ->
CLEAR
: WRITE ->
BIST<31:0>
: READ ->
REG 22 -> Controller Clock Pre-divider (CCLK_DIV) Reading REG 22 returns previously written values for all defined register bits unless otherwise noted. Reset value in bold text. ADR 0x16 Name CCLK_DIV Bit 7 RESV'D Bit 6 RESV'D Bit 5 RESV'D Bit 4 RESV'D Bit 3 CCD<3> Bit 2 CCD<2> Bit 1 CCD<1> Bit 0 CCD<0>
CCD<3:0>
: WRITE ->
0x0, Controller Clock = DACCLK / 16 0x1, Controller Clock = DACCLK / 32 0x2, Controller Clock = DACCLK / 64 ... 0xF, Controller Clock = DACCLK / 524288 NOTE: The 100MHz to 1.2GHz DACCLK must be divided to less than 10MHz for correct operation. CCD<3:0> must be programmed to divide the DACCLK so that this relationship is not violated. Controller Clock = DACCLK / ( 2 ^ ( CCD<3:0> + 4 ))
REG 31 -> VERSION Reading REG 31 returns previously written values for all defined register bits unless otherwise noted. Reset value in bold text. ADR 0x1F VER<5:0> Name VERSION : READ -> Bit 7 VER<5> Bit 6 VER<4> Bit 5 VER<3> Bit 4 VER<2> Bit 3 VER<1> Bit 2 VER<0> Bit 1 RES10 Bit 0 RES12
Version number (part ID), 00001, Revision 1, initial release 00, 14-bit DAC 01, 12-bit DAC 10, 10-bit DAC
RES10 (msb) RES12 (lsb)
: READ ->
Rev. PrJ | Page 18 of 42
Preliminary Technical Data
GENERAL DESCRIPTION
The AD9736/35/34 are 14/12/10-bit DACs which run at an update rate up to 1.2GSPS. Input data can be accepted up to the full 1.2GSPS rate or a 2x interpolation filter may be enabled (2x mode) allowing full-speed operation with a 600MSPS input data rate. DATA and DATACLK_IN inputs are parallel LVDS meeting the IEEE reduced swing LVDS specifications with the exception of input hysteresis. The DATACLK_IN input runs at one half the input DATA rate in a double data rate (DDR) format. Each edge of DATACLK_IN is used to transfer DATA into the AD9736 as shown in Figure 25. The DACCLK (pins E1, F1) directly drives the DAC core to minimize clock jitter. It is also divided by two (1x and 2x mode) then output as the DATACLK_OUT. The DATACLK_OUT signal is used to clock the data source. The DAC expects DDR LVDS data (DB<13:0>) aligned with the DDR input clock (DATACLK_IN) from a circuit similar to the one shown in Figure 35. Clock relationships are shown in Table 6.
MODE 1x 2x DACCLK 1.2GHz 1.2GHz DATACLK OUT 600MHz 600MHz DATACLK IN 600MHz 300MHz DATA 1.2GSPS 600MSPS
AD9736/AD9735/AD9734
Serial Peripheral Interface
The AD9736 serial port is a flexible, synchronous serial communications port allowing easy interface to many industrystandard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI(R) and Intel(R) SSR protocols. The interface allows read/write access to all registers that configure the AD9736. Single or multiple byte transfers are supported, as well as MSB first or LSB first transfer formats. The AD9736's serial interface port can be configured as a single pin I/O (SDIO) or two unidirectional pins for in/out (SDIO/SDO).
SDO (Pin G14) SDIO (Pin F14) SCLK (Pin G13) CSB (Pin F13) Figure 18. AD9736 SPI Port AD9736 SPI Port
Table 6. AD9736 Clock Relationships
Maintaining correct alignment of data and clock is a common challenge with high-speed DACs, complicated by changes in temperature and other operating conditions. The AD9736 simplifies this high-speed data capture problem with two adaptive closed-loop timing controllers. One timing controller manages the LVDS data and data clock alignment (LVDS controller) and the other manages the LVDS data and DACCLK alignment (SYNC controller). The LVDS controller locates the data transitions and delays the DATACLK_IN so that its transition is in the center of the valid data window. The SYNC controller manages the FIFO that moves data from the LVDS DATACLK_IN domain to the DACCLK domain. Both controllers can be operated in manual mode under external processor control, surveillance mode where error conditions generate external interrupts or automatic mode where errors are automatically corrected. The LVDS and SYNC controllers include moving average filtering for noise immunity and variable thresholds to control their activity. Normally the controllers can be set to run in automatic mode and they will make any necessary adjustments without dropping or duplicating samples sent to the DAC. Both controllers require initial calibration prior to entering automatic update mode. Control of the AD9736 functions is via the serially programmed registers listed in Table 5.
The AD9736 may optionally be configured via external pins rather than the serial interface. When the PIN_MODE input (pin L1) is high the serial interface is disabled and its pins are reassigned for direct control of the DAC. Specific functionality is described in the PIN Mode section.
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communication cycle with the AD9736. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9736, coincident with the first eight SCLK rising edges. The instruction byte provides the AD9736 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9736. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9736 and the system controller. Phase 2 of the communication cycle is a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. Using one multibyte transfer is the preferred method. Single byte data transfers are useful to reduce CPU overhead when register access requires one byte only. Registers change immediately upon writing to the last bit of each transfer byte. CSB can be raised after each sequence of 8 bits (except the last byte) to stall the bus. The serial transfer will resume when CSB is lowered. Stalling on non-byte boundaries will reset the SPI.
Rev. PrJ | Page 19 of 42
AD9736/AD9735/AD9734
SHORT INSTRUCTION MODE (8-BIT INSTRUCTION)
The short instruction byte is shown in Table 7.
MSB I7 R/W I6 N1 I5 N0 I4 A4 I3 A3 I2 A2 I1 A1 LSB I0 A0
Preliminary Technical Data
should stay low during the entire communication cycle. SDIO--Serial Data I/O. Data is always written into the AD9736 on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by SDIO_DIR at REG00, bit 7. The default is Logic 0, which configures the SDIO pin as unidirectional. SDO--Serial Data Out. Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9736 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state.
Table 7. SPI Instruction Byte
R/W, Bit 7 of the instruction byte, determines whether a read or a write data transfer will occur after the instruction byte write. Logic high indicates read operation. Logic 0 indicates a write operation. N1, N0, Bits 6 and 5 of the instruction byte, determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in Table 8. A4, A3, A2, A1, A0, Bits 4, 3, 2, 1, 0 of the instruction byte, determine which register is accessed during the data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the AD9736 based on the LSBFIRST bit (REG00, bit 6).
N1 0 0 1 1 N2 0 1 0 1 Description Transfer 1 Byte Transfer 2 Bytes Transfer 3 Bytes Transfer 4 Bytes
Table 8. Byte Transfer Count
MSB/LSB TRANSFERS
The AD9736 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by LSBFIRST at REG00, bit 6. The default is MSB first (LSBFIRST = 0). When LSBFIRST = 0 (MSB first) the instruction and data bytes must be written from most significant bit to least significant bit. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes should follow in order from high address to low address. In MSB first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communication cycle. When LSBFIRST = 1 (LSB first) the instruction and data bytes must be written from least significant bit to most significant bit. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. The serial port internal byte address generator increments for each byte of the multibyte communication cycle. The AD9736 serial port controller data address will decrement from the data address written toward 0x00 for multibyte I/O operations if the MSB first mode is active. The serial port controller address will increment from the data address written toward 0x1F for multibyte I/O operations if the LSB first mode is active.
LONG INSTRUCTION MODE (16-BIT INSTRUCTION)
The long instruction bytes are shown in Table 7.
MSB I15 R/W I7 A7 I14 N1 I6 A6 I13 N0 I5 A5 I12 A12 I4 A4 I11 A11 I3 A3 I10 A10 I2 A2 I9 A9 I1 A1 LSB I8 A8 I0 A0
Table 9. SPI Instruction Byte
If LONG_INS = 1 (REG00, bit 4) the instruction byte is extended to two bytes where the second byte provides an additional 8 bits of address information. Addresses 0x00 - 0x1F are equivalent in short and long instruction modes. The AD9736 does not use any addresses greater than 31 (0x1F) so always set LONG_INS = 0.
NOTES ON SERIAL PORT OPERATION SERIAL INTERFACE PORT PIN DESCRIPTIONS
SCLK--Serial Clock. The serial clock pin is used to synchronize data to and from the AD9736 and to run the internal state machines. SCLK's maximum frequency is 20 MHz. All data input to the AD9736 is registered on the rising edge of SCLK. All data is driven out of the AD9736 on the rising edge of SCLK. CSB--Chip Select. Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. The SDO and SDIO pins will go to a high impedance state when this input is high. Chip select The AD9736 serial port configuration is controlled by REG00, bits 4, 5, 6 and 7. It is important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register may occur during the middle of communication cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. The same considerations apply to setting the software reset, RESET (REG00, bit 5). All registers are set to their default values EXCEPT REG00 and REG04 which remain unchanged. Use of only single byte transfers when changing serial port
Rev. PrJ | Page 20 of 42
Preliminary Technical Data
configurations or initiating a software reset is highly recommended. In the event of unexpected programming sequences the AD9736 SPI may become inaccessible. For example, if user code inadvertently changes the LONG_INS bit or LSBFIRST bit the following bits may have unexpected results. The SPI can be returned to a known state by writing an incomplete byte (1-7 bits) of all zeroes followed by three bytes of 0x00. This will return to MSB first short instructions (REG00 = 0x00) so the device may be reinitialized.
INSTRUCTION CYCLE CSB DATA TRANSFER CYCLE
AD9736/AD9735/AD9734
PIN MODE OPERATION
When the PIN_MODE input (pin L1) is set high, the SPI port is disabled. The SPI port pins are remapped as shown in Table 10. The function of these pins is described in Table 11. The remaining PIN_MODE register settings are shown in Table 5, the SPI register map.
Pin Number E13 F13 G13 E14 F14 G14 PIN_MODE = 0 IRQ CSB SCLK RESET SDIO SDO PIN_MODE = 1 UNSIGNED 2X FSC0 PD FIFO FSC1
SCLK
SDIO
R/W N0 N1
A0 A1
A2 A3 A4 D7 D6N D5N
D30 D20 D10 D00
Table 10. SPI_MODE vs. PIN_MODE Inputs
SDO
D7 D6N D5N
D30 D20 D10 D00
Pin UNSIGNED 2X
Figure 19. Serial Register Interface Timing MSB First
INSTRUCTION CYCLE CSB DATA TRANSFER CYCLE
SCLK
FSC1, FSC0
A0 A1 A2 A3 A4 N1 N0 R/W D0 D1 0 D20 D4N D5N D6N D7N
SDIO
PD FIFO
SDO
D0D10 D20
D4N D5N D6N D7N
Function 0, Two's complement input data format 1, Unsigned input data format 0, Interpolation disabled 1, Interpolation = 2x enabled 00, Sleep mode 01, 10mA full scale output current 10, 20mA full scale output current 11, 30mA full scale output current 0, Chip enabled 1, Chip in power down state 0, Input FIFO disabled 1, Input FIFO enabled
Table 11. PIN_MODE Input Functions
Figure 20. Serial Register Interface Timing LSB First
tDS
CSB
tSCLK
tPWH
SCLK
tPWL
Care must be taken when using PIN_MODE since only the control bits shown in Table 11 can be changed. If the remaining register default values are not suitable for the desired operation PIN_MODE cannot be used.
03152-PrD-006
tDS
SDIO
tDH
INSTRUCTION BIT 6
INSTRUCTION BIT 7
Figure 21. Timing Diagram for SPI Register Write
CSB
SCLK tDNV SDIO I1 I0 D7 D6
tDV D5
Figure 22. Timing Diagram for SPI Register Read
After the last instruction bit is written to the SDIO pin the driving signal must be set to a high impedance in time for the bus to turn around. The serial output data from the AD9736 will be enabled by the falling edge of SCLK. This causes the first output data bit to be shorter than the remaining data bits as shown in Figure 22.
Rev. PrJ | Page 21 of 42
AD9736/AD9735/AD9734
AD9736 DATA INTERFACE CONTROLLERS
There are 2 internal controllers that can be utilized in the operation of the AD9736. The first controller helps maintain optimum LVDS data sampling and the second controller helps maintain optimum synchronization between the DACCLK and the incoming data. The LVDS controller is responsible for optimizing the sampling of the data from the LVDS bus (DB13:0) while the SYNC controller resolves timing problems between the DAC_CLK (CLK+, CLK-) and the DATACLK. A block diagram of these controllers is shown in Figure 23. The controllers are clocked with a divided down version of the DAC_CLK. The divide ratio is set utilizing the controller clock predivider bits (CCD<3:0>) located at REG22 bits 3:0 to generate the controller clock as follows: Controller Clock = DAC_CLK / ( 2 ^ ( CCD<3 :0> + 4 )) NOTE: The controller clock may not exceed 10MHz for correct operation. Until CCD<3:0> has been properly programmed to meet this requirement the DAC output may not be stable. The LVDS and SYNC controllers can be independently operated in 3 different modes via SPI port REG06 and REG08. 1. 2. 3.
Preliminary Technical Data
Manual Mode Surveillance Mode Auto Mode
In manual mode all of the timing measurements and updates are externally controlled via the SPI. In surveillance mode each controller takes measurements and calculates a new "optimal" value continuously. The result of the measurement can be passed through an averaging filter before evaluating the results for increased noise immunity. The filtered result is compared to a threshold value set via REG06 and REG08 of the SPI port. If the error is greater then the threshold, an interrupt is triggered and the controller stops. REG01 of the SPI port controls the interrupts with bits 3 and 2 enabling the respective interrupts and bits 7 and 6 indicating the respective controller's interrupt. If an interrupt is enabled it will also activate the AD9736's IRQ pin. In order to clear an interrupt the interrupt enable bit of the respective controller must be set to a zero for at least one controller clock cycle (controller clock < 10MHz). Auto mode is almost identical to surveillance mode. Instead of triggering an interrupt and stopping the controller, the controller automatically updates its settings to the newly calculated "optimal" value and continues to run.
DACCLK DATACLK_OUT CLK Control LVDS Controller DATACLK_IN DB<13:0> LVDS SAMPLE LOGIC SYNC Controller SYNC LOGIC DAC FIFO
Data Source i.e. FPGA
Figure 23.AD9736 Internal Synchronization Engine
Rev. PrJ | Page 22 of 42
Preliminary Technical Data
AD9736 LVDS Sample Logic
A simplified diagram of the AD9736 LVDS data sampling engine is shown in Figure 24, with the timing relationships shown in Figure 25. The incoming LVDS data is latched by the DATA SAMPLING SIGNAL (DSS) which is derived from DATACLK_IN. The LVDS controller delays DATACLK_IN to create the DATA SAMPLING SIGNAL (DSS) which is adjusted to sample the LVDS data in the center of the valid data window. The skew between the DATACLK_IN and the LVDS data bits (DB<13:0>) must be minimal (t1 and t2 in Figure 25) for proper operation. Therefore, it is recommended that the DATACLK_IN be generated in the same manner as the LVDS data bits (DB<13:0>) with the same driver and data lines (i.e. it should just be another LVDS data bit running a constant 01010101... sequence, as shown in Figure 35).
AD9736/AD9735/AD9734
SAMPLING SIGNAL (CSS) is controlled by MHD3:0 (REG04, bits 3:0). DATACLK_IN transitions must be time aligned with the LVDS data (DB<13:0>) transitions. This allows the CLOCK SAMPLING SIGNAL (CSS, derived from the DATACLK_IN), to find the valid data window of DB<13:0> by locating the DATACLK_IN edges. The latching (rising) edge of CSS is initially placed using bits SD<3:0> and can then be shifted to the left using MSD<3:0> and to the right using MHD<3:0>. When CSS samples the DELAYED CLOCK SIGNAL (DCS) and the result is a 1, (which can be read back via the CHECK bit at REG05, bit 0) then the sampling is occurring in the correct data cycle. In order to find the leading edge of the data cycle, increment MSD (Measured Set-up Delay) until CHECK goes low. In order to find the trailing edge, increment MHD (Measured Hold Delay) until CHECK goes low. Always set MHD = 0 when incrementing MSD and vice-versa. Note: The incremental units of SD, MSD, and MHD are in units of real time, not fractions of a clock cycle. At this time, the delay from each increment of these bits has not been fully characterized. Over process, voltage, and temperature, each increment may introduce between 25 and 100ps of delay with a nominal target of 80ps.
DB<13:0>
LVDS RX
FF
D1
DATA SAMPLING SIGNAL SD<3:0> Sample Delay DATACLK IN LVDS RX MSD<3:0> Delay MHD<3:0> Delay
FF
D2
OPERATING THE LVDS CONTROLLER IN MANUAL MODE VIA THE SPI PORT
The manual operation of the LVDS controller allows the user to step through both the set-up and hold delays to calculate the optimal sampling delay (i.e. center of the data eye). With SD<3:0> and MHD<3:0> set to zero, increment the set-up time delay (MSD<3:0>, REG04, bits 7:4) until the check bit (REG05, bit 0) goes low and record this value. This locates the leading DATACLK_IN (and DATA) transition as shown in Figure 26. With SD<3:0> and MSD<3:0> set to zero, increment the hold time delay (MHD<3:0>, REG04, bits 3:0) until the check bit (REG05 bit 0) goes low and record this value. This locates the trailing DATACLK_IN (and DATA) transition as shown in Figure 27. Once both DATACLK_IN edges are located the Sample Delay (SD<3:0>, REG05, bits 7:4) must be updated according to the following equation: Sample Delay = ( MHD - MSD ) / 2 After updating SD<3:0>, verify that the sampling signal is in the middle of the valid data window by adjusting both MHD then MSD with the new sample delay until the CHECK bit goes low. The new MHD and MSD values should be equal or within one unit delay if SD<3:0> was set correctly. NOTE: The Sample Delay calibration just described should be performed prior to enabling Surveillance mode or Auto mode.
DELAYED CLOCK SIGNAL FF CHECK CLOCK SAMPLING SIGNAL
Figure 24. AD9736 Internal LVDS Data Sampling Logic
LVDS SAMPLE LOGIC CALIBRATION
The internal DATA SAMPLING SIGNAL delay must be calibrated to optimize the data sample timing. Once calibrated, the AD9736 can generate an IRQ or automatically correct its timing if temperature or voltage variations change the timing too much. This calibration is done by using the delayed CLOCK SAMPLING SIGNAL (CSS) to sample the DELAYED CLOCK SIGNAL (DCS). The LVDS sampling logic can find the edges of the DATACLK_IN signal and from this measurement the center of the valid data window can be located. The internal delay line which derives the delayed DATA SAMPLING SIGNAL (DSS) from DATACLK_IN is controlled by SD3:0 (REG05, bits 7:4) while the DELAYED CLOCK SIGNAL (DCS) is controlled by MSD3:0 (REG04, bits 7:4) and the CLOCK
Rev. PrJ | Page 23 of 42
AD9736/AD9735/AD9734
t1
Preliminary Technical Data
t2 DB13:0
SAMPLE DELAY
PROP DELAY TO LATCH
DATACLK_IN
PROP DELAY TO LATCH
DATA SAMPLING SIGNAL
D1
D2 Figure 25. AD9736 Internal LVDS Data Sampling Logic Timing
set up time (ts) hold time (th)
DB<13:0>
DATACLK_IN Sample Delay , SD<3:0> CSS Samples DCS CSS with MHD<3:0> = 0 MSD<3:0> = 0 1 2 3 4 5 DCS, delayed by MSD<3:0> CHECK = 1 1 1 1 1 0 CHECK = 1
Figure 26. Set-Up Delay Measurement
set up time (ts) hold time (th)
DB<13:0>
DATACLK_IN Sample Delay, SD<3:0> MHD<3:0> = 0 1 2 3 4 5 CSS Samples DCS CSS, delayed by MHD<3:0>
DCS with MSD<3:0> = 0 CHECK = 1 1 1 1 1 0 CHECK = 1
Figure 27. Hold Delay Measurement
Rev. PrJ | Page 24 of 42
Preliminary Technical Data
OPERATING THE LVDS CONTROLLER IN SURVEILLANCE AND AUTO MODE
In surveillance mode, the controller searches for the edges of the data eye in the same manner as above in the manual mode of operation and triggers an interrupt if the CLOCK SAMPLING SIGNAL (CSS) has moved more than the threshold value set by LTHR<1:0> (REG06, bits 1:0). There is an internal filter which averages the set-up and hold time measurements to filter out noise and glitches on the clock lines. Average Value = ( MHD - MSD ) / 2 New Average = Average Value + ( Delta Average / 2 ^ LFLT<3:0> ) If an accumulating error in the Average Value causes it to exceed the Threshold value (LTHR<1:0>) an interrupt will be issued. The maximum allowable value for LFLT<3:0> is 12. In surveillance mode, the ideal sampling point should first be found using manual mode and applied to the sample delay registers. The user should then set the threshold and filter values depending on how far the CSS signal is allowed to drift before an interrupt occurs. Then set the surveillance bit high (REG06, bit 7) and monitor the interrupt signal either via the SPI port read back (REG01, bit 3) or the IRQ pin. In auto mode, the same steps should be taken to set up the sample delay, threshold and filter length. In order to run the controller in auto mode both the LAUTO (REG06, bit 6) and LSURV (REG06, bit 7) bits need to be set to 1. In AUTO mode the LVDS interrupt should be set low (REG01, bit 7) to allow the Sample Delay to be automatically updated if the threshold value is exceeded.
AD9736/AD9735/AD9734
between the DACCLK and the DATACLK_IN clock domains. The SYNC Controller writes data from DB<13:0> into an eight word memory based on a cyclic write counter clocked by the CLOCK SAMPLING SIGNAL (CSS) which is a delayed version of DACCLK_IN. The data is read out of the memory based on a second cyclic read counter clocked by DACCLK. The eight word deep FIFO shown in Figure 28 provides sufficient margin to maintain proper timing under most conditions. The SYNC logic is designed to prevent the read and write pointers from crossing. If the timing drifts far enough to require an update of the phase offset (PHOF<1:0>) two samples will be duplicated or dropped. Figure 29 shows the timing diagram for the SYNC logic.
SYNC LOGIC AND CONTROLLER OPERATION
The relationship between the readout pointer and the write pointer will initially be unknown since the startup relationship between DACCLK and DATACLK_IN is unknown. The SYNC logic measures the relative phase between the two counters with the zero detect block and the Flip Flop in Figure 5 above. The relative phase is returned in FIFOSTAT<2:0> (REG07, bits 6:4) and SYNC logic errors are indicated by FIFOSTAT<3> (REG07, bit 7). If FIFOSTAT<2:0> returns a value of zero or seven it signifies that the memory is sampling in a critical state (read and write pointers are close to crossing). If the FIFOSTAT<2:0> returns a value of 3 or 4 it signifies the memory is sampling at the optimal state (read and write pointers are farthest apart). If FIFOSTAT<2:0> returns a critical value the pointer can be adjusted with the phase offset PHOF<1:0> (REG07, bits 1:0). Due to the architecture of the FIFO the phase offset can only adjust the read pointer in steps of two.
OPERATING IN MANUAL MODE
Allow DACCLK and DATACLK_IN to stabilize then enable FIFO mode (REG00, bit 2). Read FIFOSTAT<2:0> (REG07, bits 6:4) to determine if adjustment is needed. For example if FIFOSTAT<2:0> = 6 the timing is not yet critical but it is not optimal. To return to an optimal state (FIFOSTAT<2:0> = 4) the PHOF<1:0> (REG07, bits 1:0) needs to be set to 1. Setting PHOF<1:0> = 1 effectively increments the read pointer by 2. This causes the write pointer value to be captured two clocks later decreasing FIFOSTAT<2:0> from 6 to 4.
AD9736 SYNC Logic and Controller
A FIFO structure is utilized to synchronize the data transfer
8 Word Memory M0
DAC<13:0>
DB<13:0> M7 ZD
FF PHOF<1:0> DACCLK
FIFOSTAT<2:0>
CSS
Write Counter
Adder Read Counter
Figure 28. SYNC Logic Block Diagram
Rev. PrJ | Page 25 of 42
AD9736/AD9735/AD9734
OPERATION IN SURVEILLANCE AND AUTO MODES
Once FIFOSTAT<2:0> has been manually placed in an optimal state the AD9736 SYNC logic can be run in Surveillance or Auto mode. To start, turn on Surveillance mode by setting SSURV = 1 (REG08, bit 7) then enable the sync interrupt (REG01, bit 2). If STRH<0> = 0 (REG08, bit 0) an interrupt will occur if FIFOSTAT<2:0> = 0 or 7. If STRH<0> = 1 (REG08, bit 0) an interrupt will occur if FIFOSTAT<2:0> = 0, 1, 6 or 7. The interrupt can be read at REG01, bit 6 at the AD9736 IRQ pin. To enter Auto mode, complete the preceding steps then set SAUTO
Preliminary Technical Data
= 1 (REG09, bit 6). Next set the SYNC interrupt = 0 (REG01, bit 2), to allow the phase offset (PHOF<1:0>) to be automatically updated if FIFOSTAT<2:0> violates the threshold value. The FIFOSTAT signal is filtered to improve noise immunity and reduce unnecessary phase offset updates. The filter operates with the following algorithm: FIFOSTAT = FIFOSTAT + Delta FIFOSTAT / 2 ^ SFLT<3:0> Where 0 <= SFLT<3:0> <= 12. Values greater than 12 are set to 12.
DACCLK INTERNAL_DELAY DATACLK_OUT EXTERNAL_DELAY DATACLK_IN DATA_IN
A B C D E F G H I J K L M N O P Q R
SAMPLE_HOLD SAMPLE_SETUP SAMPLE_DELAY CSS1 D1 CSS2 D2 WRITE_PTR1 M0 M1 M2 M3 M4 M5 M6 M7 READ_PTR1 FIFOSTAT DAC_DATA
4 4 5 6 7 0 1 2 3 4 5 6 7 0 1 B D F H J L N P A C E G I K M O Q
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
Safe Zone
A
Error Zone
I
B
J
C
K
Data `A' can be safely read from the FIFO in the Safe Zone. In the Error Zone, the pointers may briefly overlap due to clock jitter or
D
E
F
FIFOSTAT is set equal to the L write pointer each time the M read pointer changes from 7 to 0.
G
H
0
1
2
3
4
4
4
A
B
C
D
E
F
G
H
I
J
K
L
M
Figure 29. SYNC Logic Timing Diagram
Rev. PrJ | Page 26 of 42
Preliminary Technical Data
AD9736 DIGITAL BUILT-IN SELF TEST
BIST may be used to validate data transfer to the AD9736 in addition to final ATE device verification. There are 4 BIST signatures that can be read back using Registers 18-21 based on the setting of the BIST selection bits (REG17, bits 7:6) as shown in Table 12.
1 - LVDS Phase 1 2 - LVDS Phase 2 3 - SYNC Phase 1 4 - SYNC Phase 2 SEL<1> 0 0 1 1
Table 12. BIST Selection Bits
AD9736/AD9735/AD9734
memory, it is important to put the correct idle value on the DATA inputs to flush the memory prior to reading the BIST signature. Placing the idle value on the data inputs also allows the BIST to be setup while the DAC clock is running. The idle value should be all zeroes in unsigned mode (0x0000) and all zeroes except for the MSB in two's complement mode (0x2000). The BIST consists of two stages; the first stage is after the LVDS receiver and the second stage is after the FIFO stage. The first BIST stage verifies correct sampling of the data from the LVDS bus while the second BIST stage verifies correct synchronization between the DAC_CLK domain and the DATA_CLK domain. The BIST vector is generated using 32 bit LFSR signature logic. Since the internal architecture is a two bus parallel system there are two 32-bit LFSR signature logic blocks on the both the LVDS and SYNC blocks. Figure 30 shows where the LVDS and SYNC phases are located.
SEL<0> 0 1 0 1
The BIST signature returned from the AD9736 will depend on the input DATA during the test. Since the filters in the DAC have
SYNC Logic D1 DB<13:0> DATACLK_IN LVDS RX Figure 24 D2
LVDS BIST PH1
FIFO
2x
SYNC BIST PH1
DAC
LVDS BIST PH2
SYNC BIST PH2
SPI Port
Figure 30. Block Diagram Showing LVDS and SYNC Phase 1 and Phase 2
BIST OPERATION
The internal signature generator processes the input data to create the BIST signatures. An external program which implements the same algorithm may be used to generate the expected signature for comparison. A Matlab routine can be provided upon request to perform this function. Clock the test vector in as described below and compare the signature register values to the expected value to verify correct operation and input data capture. With all clocks running: 1. 2. Apply the idle vector to the data inputs (0x0000 if unsigned, 0x2000 if two's complement) for 1024 clocks, Set LVDS_EN (REG17, bit 2) and SYNC_EN (REG17, bit 1) high,
Rev. PrJ | Page 27 of 42
3. 4. 5. 6. 7. 8.
Set CLEAR (REG17, bit 0) high, Set CLEAR low to clear the BIST signature register, Clock the BIST vector into the LVDS data inputs, After the BIST vector is complete, return the inputs to the idle vector value, Set LVDS_EN (REG17, bit 2) and SYNC_EN (REG17, bit 1) low, Set the desired SEL<1:0> bits and read back the four BIST signature registers (REG18, 19, 20 and 21).
When the DAC is in 1x mode, the signature at SYNC BIST, Phase 1 should equal the signature at LVDS BIST, Phase 1. The same is true for Phase 2. BIST does not support 2x mode.
AD9736/AD9735/AD9734
AD9736 ANALOG CONTROL REGISTER
The AD9736 includes some registers for optimizing its analog performance. These registers include temperature trim for the bandgap, noise reduction in the output current mirror and output current mirror headroom adjustments.
Preliminary Technical Data
MIRROR ROLL OFF FREQUENCY CONTROL
With MSEL<1:0> (REG14, bits 7:6) the user can adjust the noise contribution of the internal current mirror to optimize the 1/F noise. Figure 32 shows MSEL vs. the 1/F noise with 20mA FullScale current into a 50ohm resistor.
BANDGAP TEMPERATURE CHARACTERISTIC TRIM BITS
Using TRMBG<2:0> (REG14, bits 2:0) the temperature characteristic of the internal bandgap can be trimmed to minimize the drift over temperature as shown in Figure 31.
Figure 32. 1/F Noise With Respect to MSEL Bits
HEADROOM BITS
HDRM<7:0> (REG15, bits 7:0) is for internal evaluation and it is not recommended to change them from their default reset values.
Figure 31. BANDGAP Temperature Characteristic for Various TRMBG Values
It is important to note that the temperature changes are sensitive to process variations and the above plot may not be representative of all fabrication lots. Optimum adjustment requires measurement of the device operation at two temperatures and development of a trim algorithm to program the correct TRMBG<2:0> values in external non-volatile memory.
Rev. PrJ | Page 28 of 42
Preliminary Technical Data
VOLTAGE REFERENCE
The AD9736 output current is set by a combination of digital control bits and the I120 reference current as shown in Figure 33.
AD9736/AD9735/AD9734
The full scale output current range is 10mA to 30mA for register values from 0x000 to 0x3FF. The default value of 0x200 generates 20mA full scale. The typical range is shown in Figure 34.
35 30
AD9736
IFS (ma)
Vbg 1.2V Vref I120 1nF 10k I120
25
FSC<9:0>
DAC
20 15 10
Current Scaling
Ifull-scale
5 0 0 200 400 600 800 1000 DAC gain code
Figure 33. Voltage Reference Circuit
Figure 34. IFS vs. DAC Gain Code
The reference current is obtained by forcing the bandgap voltage across an external 10kohm resistor from I120 (pin B14) to ground. The 1.2V nominal bandgap voltage (Vref) will generate a 120uA reference current in the 10k resistor. This current is adjusted digitally by FSC<9:0> (REG02, REG03) to set the output full scale current IFS:
VREF (pin C14) must be bypassed to ground with a 1nF capacitor. The bandgap voltage is present on this pin and may be buffered for use in external circuitry. The typical output impedance is near 5kohms. If desired, an external reference may be used to overdrive the internal reference by connecting it to the VREF pin. IPTAT (pin D14) is used for factory testing. It may be left floating (preferred) or tied to analog ground. It will output a current which is proportional to absolute temperature. The nominal output is approximately 10uA at 25C. The slope is approximately 20nA per degree C.
I FS =
Vref 192 x 72 + x FSC < 9 : 0 > R 1024
Rev. PrJ | Page 29 of 42
AD9736/AD9735/AD9734
APPLICATIONS INFORMATION
FPGA/ASIC DAC DRIVER REQUIREMENTS
To achieve data synchronization using the high speed capability of the AD9736, ADI recommends the configuration in Figure 35 for the FPGA/ASIC driving the digital inputs. Using the Double Data Rate DATACLK_OUT, this configuration will generate the LVDS DATACLK_IN to drive the AD9736 at the DDR rate. The circuit also synchronizes the DATACLK_IN and the digital input data (DB<13:0>) as required by the AD9736. The synchronization engine in the AD9736 then uses DATACLK_IN to generate the internal CLOCK SAMPLING SIGNAL to capture the incoming data via the Manual, Surveillance or Auto mode. To operate in 2x mode, the circuit in Figure 35 must be modified to include a divide-by-two block in the DATACLK_OUT path. Without this additional divider the DATA and DATACLK_IN will be running 2x too fast. DATACLK_OUT is always DACCLK/2.
Preliminary Technical Data
Figure 35. Recommended FPGA/ASIC Configuration for Driving AD9736 Digital Inputs, 1x Mode
DATACLK_OUT+ DATA1 DATA2 A B C D E
D1
A
C
D2
B
D
DB
A
B
C
DATACLK_IN+
Figure 36. FPGA/ASIC Timing for Driving AD9736 Digital Inputs, 1x Mode
TIMING ERROR BUDGET
The following components make up the timing error budget for the AD9736: 1. 2. AD9736 DATACLK_OUT jitter AD9736 DATACLK_IN jitter
3. 4. 5. 6.
DB13:0 jitter DB13:0 skew from data source DB13:0 receiver skew margin (board + AD9736 internal delays) DB13:0 to DATACLK_IN skew from data source
Rev. PrJ | Page 30 of 42
4
R EV IS IO N S
3
2
1
33DIG
A S o u r c e d a ta fr o m g i g a d a c b g a r e v b . 0 3 0 8 .2 8
L6
F E R R I TE
RED T P4
R EV
D E SC R IPT IO N
DA T E
A PP R O V E D
JR M
D
A C AS E
T B1 C 14 1 0UF 6 .3 V
1
L C 1 21 0
VDD33
D
VSS
BL K TP5 TP7 R ED
T B1
2
VSS
Preliminary Technical Data
L7
F E R R IT E
L C 1 21 0
VDD18B
A C A SE
C
T P 13 BLK
C 22 1 0U F 6 .3 V
C VSS VDD18A
18DIG
L5
F E R R IT E
RED T P6
AD9736 EVALUATION BOARD SCHEMATICS
T B1
3
L C 1 21 0
A C A SE
C 18 1 0U F 6 .3 V
VSS
BLK T P 14 JP 1
T B1
4
VSS VSS VSSA
UN DE R D UT
Figure 37. Power Supply Inputs for AD9736 Evaluation Board, Rev C
Rev. PrJ | Page 31 of 42
TP1 RED
B VDDA33
A C A SE
33ANA
C1 1 0U F 6 .3 V
L1
F E R R IT E
T B2
1
L C 1 21 0
B
VSSA
BL K TP3 TP9 R ED
T B2
2
VSSA P O W E R IN P U T F IL T E R S
18ANA VDDC
L3
F E R R IT E
T B2
3
L C 1 21 0
A C AS E
C 10 1 0UF 6 .3 V
A VSSA
BL K TP11
VSSA
L4
F E R R IT E
S IZE
FS C M N O
D R A W IN G N U M B E R
REV
A
W I L M IN G T O N M A N U F A C T U R IN G
8 0 4 W O B UR N ST R EE T W IL M IN G T ON , MA 0 1 88 7 DR A W N B Y: AP P R OV E D B Y : SC A L E NO N E D O N O T SC A LE
T B2
4
L C 1 21 0
B
H YDROGEN
F IL E D A T E = 0 4 0 5 .1 9
C
SHE ET 1 0 F 5
AD9736/AD9735/AD9734
4
3
2
1
4 VDD18B
0 .1 U F
CC 0603 CC 0603
3
2
1
IN IP
1NF C25 H1 VDD 1 VDD 2 VDD 3 VDD14 VDD13 VDD12 VDD11 VDD10 VDD9 VSS20 VSS19 VSS18 VSS17 VSS5 VSS6 M3 M4 M5 M6 K2 1 K1 L2 L1 M2 M1 N1 P1 N2 P2 WHT T P10 N3 P3 VSS7 VSS8 VSS9 VSS10 VSS21 NC K1 VSS22 S P I_ M O D E LV D S 0N LV D S 0P LV D S 1N LV D S 1P LV D S 2N LV D S 2P LV D S 3N VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 L VDS13N L VDS13P L VDS12N L VDS12P L VDS11N L VDS11P L VDS10N L VDS10P LV D S 9N LV D S 9P LV D S 8N VDD 4 VDD 5 VDD 6 VDD 7 VDD 8 VSS1 VSS2 VSS3 VSS4 H Y D R O G E N VD D 1 6 H2 H3 C7
CC0603 ACASE
D
C24 H 14 H 13 H 12 H 11 J14 J13 J12 J11 K 11 K 12 L9 L 10 L 11 L 12 L6 M9 M 10 M 11 M 12 K 13 K 14 L 13 L 14 M 13 M 14 N 14 P14 N 13 P13 N 12 P12 VDD15 A7 IN1 TO P IP 2 IP 3 IP 4 VSSA3313 C3 6.3V D NP
AC ASE
C23 4 .7 U F 6 .3 V
D
IP 1 B8 C8 D8 A9 C4 J2 J3 J4 K3 0 .1 U F
CC06 03 CC06 03 CC0603 CC060 3
A8
B7 IN2 IN3 H4 J1 IN4 VSSA 331 VSSA 332 VSSA3314 VSSA3315 VSSA3316 VSSA3317 VSSA3318
A CASE
C7 D7 A4 A5 A6 VSSA 333 VSSA 334 VSSA 335 VSSA 336 VSSA 337 VSSA3319 VSSA3320 VSSA3321 VSSA3322 VSSA3323 VSSA3324 VDDA 331 VDDA 332 VDDA 333 VDDA 334 VDDA 335
JP4
AD9736/AD9735/AD9734
VSSA
VSS
U1
A10 A11 B9 1NF 0.1UF 1NF C21 L4 L5 L3 K4 C2 B10 B 11 C9 C10 C11 D9 D10 D11 A12 A13 B12
RC 0603 C C0603
4 .7 U F
VDD18A
C8
C C0603
B4 B5 B6 C4 C5 VSSA 338 VSSA 339 VSSA 3310 VSSA 3311 VSSA 3312 VD DC 1 D NP R16 10K VD DC 2 VD DC 3 VD DC 4 VD DC 5 VD DC 6 VD DC 7 VDDA 337 VDDA 338 S PA R E I1 2 0 VR EF IP T A T S IG NE D_IRQ PD_RESET 2X_C SB F IF O _ S D I O
JP3
D NP
VDDA33
C20
C19 4 .7 U F 6 .3 V
C
D4 D5 D6 A1 A2 A3 B1 B13 C12 B2 C6
C C0603
C6
IRQ VSS
TP 2 W HT
C
C5
DN P
VDD33 VDD33 VSSA
C9
CC0603
1
JP15 AB3 2 JP8 AB3 2
IPTAT SPARE VSSA
.1 % 10.00K R1 TP 12 W HT T P16 WHT 1NF
B3 VDDA 336 D12 D13 A14 B14 C14 D14 E13 E1 4 F13 F14 G13 G14 E 11 E12 F 11 F12 G11
RC1206
C13
C1 C2 VD DC 8 VD DC 9 VD DC 10 VD DC 11 VSSC 1 C LK N C LK P VSSC 2 VSSC 3 VSSC 4 VSSC 5 VSSC 6 VSSC 7 VSSC 8 S H IE L D 3 S H IE L D 4 3 V S S ;5 VSSC 9 VSSC 10 VSSC 11 S H IE L D 6 HYDR O G EN G12 4 S H IE L D 2 S H IE L D 1 F SC1_SD O F SC0_SCL K WHT TP8 C3 D2 D3 D1 E1 F1 E2 E3 E4 F2 F3 F4 1N F
CC0603
Figure 38. Circuitry Local to AD9736, Evaluation Board, Rev C
Rev. PrJ | Page 32 of 42
IRQ RESET_A VREF I120 SPCSB SPSDI SPCLK SPSDO RESET SW 1 2
1
B
B
CLKN CLKP
LV D S 3P N4 P4 N5 P5 N6 P6 LV D S 4N LV D S 4P LV D S 5N LV D S 5P
LV D S 8P LV D S 7N LV D S 7P LV D S 6N LV D S 6P L L V D S C L K O U T N V D S C L K IN N
N 11 P11 N 10 P10 N9 P9
VDDC
G1 G2 G3 G4
C 11
VDD33 VDD33
DB13N DB13P DB12N DB12P DB11N DB11P DB10N DB10P DB9N DB9P DB8N DB8P DCLKNOUT DCLKPOUT
0.1UF
AC ASE CC06 03 CC0 603
LV D S CL KO U TP V D S CL KINP L L7 M7 1NF C 16 C17 N7 C15 4 .7 U F 6 .3 V P7 VDD 331 VDD 332 VDD 333 VDD 334 BO T TO M VDD 338 VDD 337 VDD 336 VDD 335
0.1UF C 13
L8 M8 N8 P8
DB0N DB0P DB1N DB1P DB2N DB2P DB3N DB3P DB4N DB4P DB5N DB5P DB6N DB6P DB7N DB7P DCLKNIN DCLKPIN
C34
CC0 603
4.7UF
ACA SE
CC0603
6.3V
C 12
U1
S H IE L D 5
DN P
A VSSA
R5 10K
VSSA
A VSS VSS VSS HYDROGEN REV C 2 OF 5
Preliminary Technical Data
4
3
2
1
Preliminary Technical Data
Figure 39. High Speed Digital I/O Connector, AD9736 Evaluation Board, Rev C
Rev. PrJ | Page 33 of 42
A B C D EXTCLK TESTOUTP TESTOUTN
AD9736/AD9735/AD9734
4 3 2 HYDROG EN REV C 3 OF 5 A 1
4
T P15 WHT
G1
Jack
G2 S2 G4 S4 G6 S6 G8 S8 G10 S10 G12 S12 G14 S14 G16 S16 G18 S18 G20 S20 G22 S22 G24 S24 G26 S26 G28 S28 G30 S30 G32 S32 G34 S34 G36
S3 G5 S5 G7 S7 G9 S9 G11 S11 G13 S13 G15 S15 G17 S17 G19 S19 G21 S21 G23 S23 G25 S25 G27 S27 G29 S29 G31 S31 G33 S33 G35 S35 G37 S37 G39 S39 G41 S41 G43 S43 G45 S45 G47 S47 G49
FCN-268 F024-G/0 D
S1
Jack
G3
3 2
S36 G38 S38 G40 S40 G42 S42 G44 S44 G46 S46 G48 S48 G50
J3
VSS 1
DB13N DB12N DB11N DB10N DB9N DB8N DCLKNOUT DCLKNIN DB7N DB6N DB5N DB4N DB3N DB2N DB1N DB0N
DB0P DB1P DB2P DB3P DB4P DB5P DB6P DB7P DCLKPIN DCLKPOUT DB8P DB9P DB10P DB11P DB12P DB13P B
C
D
4
3
2
1
D
R20
RC0603
25 25
RC0603
D
R21
CLKP
T 3A 3 P 1
RC0603
AD9736/AD9735/AD9734
4 S 6
CC0603
V S S A ;3 ,4 ,5 S M A 2 00U P
C36 0 .1 U F
CC0603
J1
ADTL1-12XX
C35 0 .1 U F
CLKN VDDC
DNP
CC0603 CC 0603
VSSA
P
N C=2
4 S 1
ETC1-1-13
RC0603
3 C26
NOTE: T1, T3 & T3B are installed, R6 & R8 = 50 ohms, R17 & R19 = 20 ohms, R161 & R162 = 0 ohms, R7 = Open
R3 1K DN P C27 1NF
CC06 03
C
T 3B R4 300
CC 0603
5
C
C38 1NF
Jumper added from T1 pin 3 to T1 pin 2
0 .1 U F
C C0603
C28
C29
VSSA
VSSA
RC0603
RC0603
RC0603
RC0603
Figure 40. Clock Input and Analog Output, AD9736 Evaluation Board, Rev C
R6 D NP
Rev. PrJ | Page 34 of 42
D NP
R C0603 RC0603
B
T2 A D T 2 -1 T -1 P 4 5 6S D NP
R C0603 RC0603
IN
R 17 T1 A D T 2 -1 T -1 P 4 5 6S P1 2 3 DNP R161
B J2
V S S A ;3 ,4 ,5 S M A 20 0U P
3 2 P1
R7 49.9 R 18 D NP R 19 3 S
NC=2
DNP 4 P 5
ETC1-1-13
R162 3 S 1
ETC1-1-13
N C=2
4 P 5 T4B
IP
1 R8 D NP T3
VSSA
Jumper Added
A
VSSA
VSSA
A
HYDROGEN 3 2 1
REV C 4 OF 5
Preliminary Technical Data
4
4
3
2
1
D
D
VDD33
JP 5
1
JP13 AB3 2
VSS
SPCSB SPI PORT VSS
JP6 2 74A C14 1 U5 U5 3
V S S ;7 V DD 3 3 ; 1 4 V S S ;7 V DD 3 3 ; 1 4
Preliminary Technical Data
VDD33
U5 1 74A C14 R11 11
V S S ;7 V D D 3 3 ;1 4 V S S ;7 V D D 3 3 ;1 4
1 U5 12
RC08 05
JP14 AB3 2 R10 13 1 2 3
RC08 05
9K P1
SPCLK
9K 4 5 6
RC08 05
C
JP9 AB3 2
C
VDD33
JP7 74A C14 74A C14 8 74A C14 U6 12 74AC14
V S S ;7 V D D 3 3 ;1 4
VSS
6 9 U5 5
V S S ;7 V DD 3 3 ; 1 4
4
10
SPSDI
U5 R12 9K 1 74A C14 JP10 AB3 2
VDD33
JP2 1
V S S ;7 V D D3 3 ; 1 4
VSS
U6 2
V S S ;7 V DD 3 3 ; 1 4
2
SPSDO
RC0603
13
R13 10K U6 3
V S S ;7 V DD 3 3 ; 1 4
RC0603
74AC 14
R 14 10K U6 4 74AC 14 U6 6
V S S ;7 V D D 3 3 ;1 4 V S S ;7 V D D 3 3 ;1 4
Figure 41. SPI Port Interface, AD9736 Evaluation Board, Rev C
1
Rev. PrJ | Page 35 of 42
JP11 AB3 2
VDD33
11 74AC14 U6 8 74AC14 10
VSS RESET_A
5
V S S ;7 V DD 3 3 ; 1 4
VDD33 B
C31
A C A SE CC0805 ACASE
B
9 74AC 14
C33
C C0805
C 30 4.7UF 6.3V
.1UF
C 32 4.7UF 6.3V
.1UF
VSS
1 JP12 AB3 2
VDD33 IRQ
L9
VSS VSS
L8 FE R RITE
LC 1210
FE R RITE
LC 1210
2
A
A
HYDROGEN 3 2 1
REV C 5 OF 5
AD9736/AD9735/AD9734
4
AD9736/AD9735/AD9734
AD9736 EVALUATION BOARD PCB LAYOUT
Preliminary Technical Data
NOTE: AD9736 is soldered directly to the PCB, the socket is not installed. Silkscreen Error: SPI PIN
Figure 42. PCB Layout Top Placement, AD9736 Evaluation Board, Rev C
Rev. PrJ | Page 36 of 42
Preliminary Technical Data
AD9736/AD9735/AD9734
Figure 43. PCB Layout Layer 1, AD9736 Evaluation Board, Rev C
Rev. PrJ | Page 37 of 42
AD9736/AD9735/AD9734
Preliminary Technical Data
Figure 44. PCB Layout Layer 2, AD9736 Evaluation Board, Rev C
Rev. PrJ | Page 38 of 42
Preliminary Technical Data
AD9736/AD9735/AD9734
Figure 45. PCB Layout Layer 3, AD9736 Evaluation Board, Rev C
Rev. PrJ | Page 39 of 42
AD9736/AD9735/AD9734
Preliminary Technical Data
Figure 46. PCB Layout Layer 4, AD9736 Evaluation Board, Rev C
Rev. PrJ | Page 40 of 42
Preliminary Technical Data
AD9736/AD9735/AD9734
Figure 47. PCB Layout Bottom Placement, AD9736 Evaluation Board, Rev C
Rev. PrJ | Page 41 of 42
AD9736/AD9735/AD9734
Preliminary Technical Data
NOTE: Special layer stack to control LVDS trace impedance.
Figure 48. PCB Fabrication Detail, AD9736 Evaluation Board, Rev C
Rev. PrJ | Page 42 of 42
PR04862-0-9/04(PrJ)
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